Ensemble RX II (HF/LF) Quadrature Clock Generator
Band: HF
Summary Build Notes
Introduction
Band Specific Components
This stage involves band-specific components and is currently configured for the HF band. If you need to configure this page for a different band, click on the "Band" tab in the menu above. This would take you to the home page, where you can select the new band and then return to this page.
General Info About the Stage
This stage divides the local oscillator output by 4 and shifts the phase of the dividend signals such that they are now one-fourth the LO frequency and 90 degrees separated in phase (i.e., in quadrature). Both signals are identical in all regards except phase. They will be used to clock the switch used in the Quadrature Sampling Detector (QSD) stage.
Theory of Operation
Stage Schematic
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Click here for full schematic
(Red dots represent the "hairpin" (or left-hand or topmost) lead of the component)
Summary Build Notes
Quadrature Clock Generator Bill of Materials
(HF band option)
(details for installation of each component are provided in the step instructions, further down the page)
| Check | Type | Category | Component | Count | Marking | Image |
|---|---|---|---|---|---|---|
| ☐ | Band-specific | Omit | omit for this band | 2 | ||
| ☐ | Capacitor | SMT 1206 | 0.1 uF | 1 | (smt) black stripe |
|
| ☐ | IC | SOIC-14 | 74AC74 Dual D FF | 1 | 74AC74 ESD!!! |
|
| ☐ | Resistor | 1/6W | 10 k 1/6W 5% | 2 | brn-blk-ora-gld |
|
| ☐ | wire | Cutoff | shunt wire (cut-off lead) | 1 |
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Detailed Build Steps
Install Voltage Divider Resistors
Pay careful attention to the orientation (S-N and N-S, respectively) of R10 and R11. Some builders have inadvertently installed these with a horizontal orientation rather than a vertical orientation.
| Check | Designation | Component (top/bottom) | Orientation | Marking | Image | Band | Notes |
|---|---|---|---|---|---|---|---|
| ☐ | R10 | 10 k 1/6W 5% (top) | S-N | brn-blk-ora-gld |
|
any | |
| ☐ | R11 | 10 k 1/6W 5% (top) | N-S | brn-blk-ora-gld |
|
any |
Install ICs and SMT Capacitors
Here, you will install U6 (to get a divide-by-4) and, if building the LF option, U12 (to get a divide-by-16); also installed will be the appropriate SMT bypass capacitors.
U6 is required for both HF and LF options; U12 is only needed for the LF option. Watch out for the potential to install U6 in the wrong set of pads!
| Check | Designation | Component (top/bottom) | Orientation | Marking | Image | Band | Notes |
|---|---|---|---|---|---|---|---|
| ☐ | C36 | 0.1 uF ((bottom)) | white pads | (smt) black stripe |
|
any | |
| ☐ | C48 | omit for this band ((bottom)) | white pads | HF | |||
| ☐ | U06 | 74AC74 Dual D FF ((bottom)) |  |
74AC74 ESD!!! |
|
any | Markings vary - look for "AC74" |
| ☐ | U12 | omit for this band ((bottom)) | HF |
Install HF Jumper
If building the HF option, omit U12 and Install the jumper wire to bypass U12 with the LO signal | Check | Designation | Component (top/bottom) | Orientation | Marking | Image | Band | Notes |
|---|---|---|---|---|---|---|---|
| ☐ | hf-jmp | shunt wire (cut-off lead) (top) | HF |
Test the Quadrature Clock Generator Stage
Quadrature Clock Generator - Current Draw
With both the USB cable and the power cable plugged in, measure the current draw in the positive power lead.
Measure the current draw with just the 12V power.
Note: the current draw will be slightly higher if you installed U12 as part of an LF option build
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Test Steps (if any)
| Step | Test Point | UOM | Nominal | Author's | Builder's |
|---|---|---|---|---|---|
| 0 | Current draw WITH USB | mA | < 18 | 9.8 | |
| 1 | Current draw NO USB | mA | < 20 | 13.7 |
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Quadrature Clock Generator - Test Voltage Divider
When performing the following tests, you must apply [pwer to the board AND plug in the USB cable. Otherwise, results will not be as expected.
Plug in USB and power the board.
Measure the voltage on the R11 hairpin; you should see 50% of the %v rail voltage.
Depending upon your DMM, your measurements may vary. What we are looking for here is roughly half the 5 volt rail.
Troubleshooting the Voltage Divider
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Test Steps (if any)
| Step | Test Point | UOM | Nominal | Author's | Builder's |
|---|---|---|---|---|---|
| 0 | R11 hairpin (WRT regular gnd) | V dc | 2.5 | 2.46 |
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Quadrature Clock Generator - Divider Pin Voltages
Power USB and 12V. Then measure the voltages on the pins (and, separately, on the pads) of U6 (74AC74). Refer to the color codes on the graphic for the voltages.
Pins 3 and 11 will not show exactly 2.5Vdc because they have the additional AC component of the local oscillator signal from C3. The important idea is - for those pins which should nominally be 2.5Vdc - you do NOT want to see 0 or 5 Vdc!
If you are building the LF option, you should perform this test on both U12 and U6; otherwise, just test U6.
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Test Steps (if any)
| Step | Test Point | UOM | Nominal | Author's | Builder's |
|---|---|---|---|---|---|
| 1 | Pin 1 | Vdc | 5 | 4.92 | |
| 2 | Pin 2 | Vdc | 2.5 | 2.45 | |
| 3 | Pin 3 | Vdc | 2 to 3 | 2.46 | |
| 4 | Pin 4 | Vdc | 5 | 4.92 | |
| 5 | Pin 5 | Vdc | 2.5 | 2.45 | |
| 6 | Pin 6 | Vdc | 2.5 | 2.45 | |
| 7 | Pin 7 | Vdc | 0 (GND) | 0 | |
| 8 | Pin 8 | Vdc | 2.5 | 2.45 | |
| 9 | Pin 9 | Vdc | 2.5 | 2.45 | |
| 10 | Pin 10 | Vdc | 5 | 4.92 | |
| 11 | Pin 11 | Vdc | 2.5 | 2.46 | |
| 12 | Pin 12 | Vdc | 2 - 3 | 2.45 | |
| 13 | Pin 13 | Vdc | 5 | 4.92 | |
| 14 | Pin 14 | Vdc | 5 | 4.92 |
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Quadrature Clock Generator - Quadrature Colck Generated Waveforms
Set your board up to oscillate at a selected center frequency, e.g., 7.100 MHz.
If you have a dual trace scope available, probe the two "QSD CLK (n)" test points and you should get a waveform similar to the one shown here.
The testpoint marked "LO Clock" will provide the Si570's output frequency or, in the case of the LF option, that frequency divided by 4 (courtesy of U12).
Your mileage may vary, depending upon the desired center frequency you select and the quality of your scope (some scopes tend to have issues with these square waves - still, the scope should show two waveforms in quadrature at the desired center frequency).
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Test Steps (if any)
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